View PCD3354A_2120552.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation supersedes data of 1996 may 09 file under integrated circuits, ic03 1996 dec 18 integrated circuits pca3354c; PCD3354A 8-bit microcontrollers with dtmf generator and 256 bytes eeprom
1996 dec 18 2 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 frequency generator 6.1 frequency generator derivative registers 6.2 melody output (p1.7/mdy) 6.3 dtmf clock divider and output (dp1.7/dco) 6.4 frequency registers 6.5 dtmf frequencies 6.6 modem frequencies 6.7 musical scale frequencies 7 eeprom and timer 2 organization 7.1 eeprom registers 7.2 eeprom latches 7.3 eeprom flags 7.4 eeprom macros 7.5 eeprom access 7.6 timer 2 8 derivative interrupts 9 timing 10 reset 11 idle mode 12 stop mode 13 summary of i/o ports and mask options 14 summary of derivative registers 15 handling 16 limiting values 17 dc characteristics 18 ac characteristics 19 package outlines 20 soldering 20.1 introduction 20.2 reflow soldering 20.3 wave soldering 20.4 repairing soldered joints 21 definitions 22 life support applications
1996 dec 18 3 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 1 features 8-bit cpu, rom, ram, eeprom and i/o; all in a 44-lead quad flat package 8 kbytes rom; 256 bytes ram 256 bytes electrically erasable programmable read only memory (eeprom) over 100 instructions (based on mab8048) all of 1 or 2 cycles 36 quasi-bidirectional i/o port lines 8-bit programmable timer/event counter 1 8-bit reloadable timer 2 three single-level vectored interrupts: C external C 8-bit programmable timer/event counter 1 C derivative; triggered by reloadable timer 2 two test inputs, one of which also serves as the external interrupt input dtmf, modem, musical tone generator reference for supply and temperature-independent tone output filtering for low output distortion (cept compatible) melody output for ringer application programmable dtmf clock divider power-on-reset stop and idle modes supply voltage: 1.8 to 6 v (dtmf tone output and eeprom erase/write from 2.5 v) cpu clock frequency: 1 to 16 mhz (3.58 mhz or 10.74 mhz for dtmf) operating ambient temperature: C - 25 to +70 c (PCD3354A) C 0 to 50 c (pca3354c) manufactured in silicon gate cmos process. 2 general description this data sheet details the specific properties of the pca3354c and PCD3354A. the shared properties of the pcd33xxa family of microcontrollers are described in the pcd33xxa family data sheet, which should be read in conjunction with this publication. the pca3354c and PCD3354A are microcontrollers oriented towards telephony applications. they include 8 kbytes rom, 256 bytes ram, 36 i/o lines, and an on-chip generator for dual tone multifrequency (dtmf), modem and musical tones. in addition to dialling, the generated frequencies can be made available as square waves for melody generation, providing ringer operation. the pca3354c and PCD3354A also incorporate 256 bytes of eeprom, permitting data storage without battery backup. the eeprom can be used for storing telephone numbers, particularly for implementing redial functions. the differences between pca3354c and PCD3354A are shown in table 1. the instruction set is similar to the mab8048 and is a sub-set of that listed in the pcd33xxa family data sheet. table 1 differences: pca3354c and PCD3354A note 1. see chapter 13, table 24. type v por ambient temp. range pca3354c ?xed at 2.0 v 0.3 v 0 to 50 c PCD3354A (1.2 to 3.6 v) 0.5 v (1) - 25 to +70 c 3 ordering information (see note 1) note 1. please refer to the order entry form (oef) for this device for the full type number to use when ordering. this type number will also specify the required program and the rom mask options. type number package name description version pca3354ch qfp44 plastic quad ?at package; 44 leads (lead length 2.35 mm); body 14 14 2.2 mm sot205-1 PCD3354Ah
1996 dec 18 4 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 4 block diagram handbook, full pagewidth med265 port 0 flip-flop port 0 buffer higher program counter lower program counter program status word memory bank flip-flops resident rom 8 kbytes decode 58888 p0.0 to p0.7 8 8 88 8 8 timer/ event counter 32 internal clock freq. 30 t1 port 1 buffer port 1 flip-flop p1.0 to p1.7/mdy 8 port 2 buffer port 2 flip-flop p2.0 to p2.3 4 4 8 8 der. port 0 flip-flop der. port 0 buffer 8 dp0.0 to dp0.7 8 dtmf-clock & melody control register 8 tone filter oscillator ram address register accumulator temporary register 1 temporary register 2 arithmetic decimal adjust control and timing xtal2 xtal1 reset ce/t0 stop idle interrupt initialize multiplexer 8 level stack (variable length) optional second register bank data store d e c o d e register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 timer interrupt external interrupt resident ram array 256 bytes derivative interrupt 8 logic unit 8 instruction register and decoder conditional branch logic ce/t0 timer flag carry acc acc bit test t1 lgf register 8 hgf register 8 sine wave generator interrupt logic 8 eeprom data transfer 8 eeprom address register 8 eeprom control register 8 timer 2 register 8 timer 2 reload register 8 eeprom 256 bytes pca3354c PCD3354A der. port 1 buffer der. port 1 flip-flop dp1.0 to dp1.7/dco f dtmf 8 8 power-on-reset v por reset fig.1 block diagram.
1996 dec 18 5 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 5 pinning information 5.1 pinning fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 pca3354ch PCD3354Ah med266 p1.0 p0.7 p0.6 p0.5 xtal2 xtal1 p0.3 p0.2 p0.1 p0.0 p2.1 p2.2 p2.3 dp0.0 dp0.1 dp0.2 dp0.4 dp0.5 dp0.7 p0.4 p1.7/mdy p1.6 p1.5 p1.4 p1.3 v dd v ss p1.2 p1.1 p2.0 tone dp0.3 dp0.6 t1 reset dp1.0 dp1.1 dp1.2 dp1.3 dp1.4 dp1.6 dp1.7/dco ce/t0 dp1.5
1996 dec 18 6 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 5.2 pin description table 2 sot205-1 package (for information on parallel i/o ports, see chapter 13) symbol pin type description p2.1 to p2.3 1 to 3 i/o 3 bits of port 2: 4-bit quasi-bidirectional i/o port dp0.0 to dp0.7 4 to 11 i/o derivative port 0: 8-bit quasi-bidirectional i/o port ce/ t0 12 i chip enable or test 0 input t1 13 i test 1/count input of 8-bit timer/event counter 1 reset 14 i reset input dp1.0 to dp1.6 15 to 21 i/o 7 bits of derivative port 1: 8-bit quasi-bidirectional i/o port dp1.7/dco 22 i/o 1 bit of derivative port 1: 8-bit quasi-bidirectional i/o port; or dtmf clock output p0.0 to p0.3 23 to 26 i/o 4 bits of port 0: 8-bit quasi-bidirectional i/o port xtal1 27 i crystal oscillator/external clock input xtal2 28 o crystal oscillator output p0.4 to p0.7 29 to 32 i/o 4 bits of port 0: 8-bit quasi-bidirectional i/o port p1.0 to p1.2 33 to 35 i/o 3 bits of port 1: 8-bit quasi-bidirectional i/o port v ss 36 p ground tone 37 o dtmf output v dd 38 p positive supply voltage p1.3 to p1.6 39 to 42 i/o 4 bits of port 1: 8-bit quasi-bidirectional i/o port p1.7/mdy 43 i/o 1 bit of port 1: 8-bit quasi-bidirectional i/o port; or melody output p2.0 44 i/o 1 bit of port 2: 4-bit quasi-bidirectional i/o port
1996 dec 18 7 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 6 frequency generator a versatile frequency generator section with built-in programmable clock divider is provided (see fig.3). the clock divider allows the dtmf section to run either with the main clock frequency (f dtmf =f xtal ) or with a third of it (f dtmf = 1 3 f xtal ) depending on the state of the divider control bit div3 (see table 5). the frequency generator includes precision circuitry for dual tone multifrequency (dtmf) signals, which is typically used for tone dialling telephone sets. the tone output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. in addition to dtmf and modem frequencies, two octaves of musical scale in steps of semitones are available. their frequencies are provided either in purely sinusoidal form on the tone output or as a square wave on the port line p1.7/mdy. the latter is typically for ringer applications in telephone sets. if no frequency output is selected the tone output is in 3-state mode. 6.1 frequency generator derivative registers 6.1.1 h igh and l ow g roup f requency r egisters table 3 gives the addresses, symbols and access types of the high group frequency (hgf) and low group frequency (lgf) registers, used to set the frequency output. table 3 hexadecimal addresses, symbols, access types and bit symbols of the frequency registers 6.1.2 c lock and m elody c ontrol r egister (mdycon) table 4 clock and melody control register, mdycon (address 13h; access type r/w) table 5 description of mdycon bits register address register symbol access type bit symbols 7 6 5 4 3 2 1 0 11h hgf w h7h6h5h4h3h2h1h0 12h lgf w l7l6l5l4l3l2l1l0 7 6 5 4 3 2 1 0 0 0 0 0 0 edco div3 emo bit symbol description 7to3 - these bits are set to a logic 0. 2 edco enable dtmf clock output. if bit edco = 0, then dp1.7/dco is a general purpose derivative port line. if bit edco = 1, then dp1.7/dco is the dtmf clock output. edco = 1 does not inhibit the port instructions for dp1.7/dco. therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. however, the port flip-flop of dp1.7/dco must remain set to avoid conflicts between dtmf clock and port outputs. 1 div3 enable dtmf clock divider. if bit div3 = 0, then the dtmf clock f dtmf =f xtal . if bit div3 = 1, then f dtmf = 1 3 f xtal . 0 emo enable melody output. if bit emo = 0, then p1.7/mdy is a standard port line. if bit emo = 1, then p1.7/mdy is the melody output. emo = 1 does not inhibit the port instructions for p1.7/mdy. therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. however, the port flip-flop of p1.7/mdy must remain set to avoid conflicts between melody and port outputs. when the hgf contents are zero while emo = 1, p1.7/mdy is in the high state.
1996 dec 18 8 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A fig.3 block diagram of the frequency generator, melody output (p1.7/mdy) and dtmf clock output (dp1.7/dco). handbook, full pagewidth mgb782 hgf register clock and melody control register lgf register internal bus 8 f xtal f dtmf 8 8 8 switched capacitor bandgap voltage reference digital sine wave synthesizer clock divider digital sine wave synthesizer switched capacitor low-pass filter dac dac rc low-pass filter tone port/melody output logic p1.7/ mdy port/clock output logic dp1.7/ dco square wave 6.2 melody output (p1.7/mdy) the melody output (p1.7/mdy) is very useful for generating musical notes when a purely sinusoidal signal is not required, such as for ringer applications. the square wave (duty cycle = 12 23 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the hgf register (table 3). however, even higher frequency notes may be produced since the low-pass filtering on the tone output is not applied to the p1.7/mdy output. this results in the minimum decimal value x in the hgf register (see equation in section 6.4) being 2 for the p1.7/mdy output, rather than 60 for the tone output. a sinusoidal tone output is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves with x < 60 will not appear at the tone output. since the melody output is shared with p1.7, the port flip-flop of p1.7 has to be set high before using the melody output. this is to avoid conflicts between melody and port outputs. the melody output drive depends on the configuration of port p1.7/mdy, see chapter 13, table 24. 6.3 dtmf clock divider and output (dp1.7/dco) the dtmf clock divider allows the dtmf part to run either with the main clock frequency (f dtmf =f xtal ) or with a third of it (f dtmf = 1 3 f xtal ) depending on the state of the divider control bit div3 in register mdycon. for low power applications, a 3.58 mhz quartz crystal or pxe resonator can be chosen together with the divide-by-one function of the clock divider. for other applications a 10.74 mhz quartz crystal or pxe resonator may be chosen together with the divide-by-three function of the clock divider. this triples the program speed of the microcontroller, thereby keeping the assumed dtmf frequency of 3.58 mhz. since a 3.58 mhz clock is needed for peripheral telephony circuits such as the analog voice scrambler/descrambler pcd4440t, a switchable dtmf clock output is provided depending on the state of the enable clock output bit edco in register mdycon.
1996 dec 18 9 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A if edco = 1 and div3 = 1 in the mdycon register: a square wave with the frequency f dtmf = 1 3 f xtal is output on the derivative port line dp1.7/dco. if edco = 1 and div3 = 0: a square wave with the frequency f dtmf =f xtal is output on the derivative port line dp1.7/dco. the melody output drive depends on the configuration of port p1.7/mdy, see chapter 13, table 24. 6.4 frequency registers the two frequency registers hgf and lgf define two frequencies. from these, the digital sine synthesizers together with the digital-to-analog converters (dacs) construct two sine waves. their amplitudes are precisely scaled according to the bandgap voltage reference. this ensures tone output levels independent of supply voltage and temperature. the amplitude of the low group frequency sine wave is attenuated by 2 db compared to the amplitude of the high group frequency sine wave. the two sine waves are summed and then filtered by an on-chip switched capacitor and rc low-pass filters. these guarantee that all dtmf tones generated fulfil the cept recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. the value 00h in a frequency register stops the corresponding digital sine synthesizer. if both frequency registers contain 00h, the whole frequency generator is shut off, resulting in lower power consumption. the frequency f of the sine wave generated from either of the frequency registers is a function of the clock frequency f xtal and the decimal value x held in the register. the equation relating these variables is: ; where 60 x 255. the frequency limitation given by x 3 60 is due to the low-pass filters which would attenuate higher frequency sine waves. 6.5 dtmf frequencies assuming an oscillator frequency f xtal = 3.58 mhz, the dtmf standard frequencies can be implemented as shown in table 6. the relationship between telephone keyboard symbols, dtmf frequency pairs and the corresponding frequency register contents are given in table 7. f f xtal 23 x 2 + () [] --------------------------------- = table 6 dtmf standard frequencies and their implementation; value = lgf, hgf contents table 7 dialling symbols, corresponding dtmf frequency pairs and frequency register contents value (hex) frequency (hz) deviation standard generated (%) (hz) dd 697 697.90 0.13 0.90 c8 770 770.46 0.06 0.46 b5 852 850.45 - 0.18 - 1.55 a3 941 943.23 0.24 2.23 7f 1209 1206.45 - 0.21 - 2.55 72 1336 1341.66 0.42 5.66 67 1477 1482.21 0.35 5.21 5d 1633 1638.24 0.32 5.24 telephone keyboard symbols dtmf freq. pairs (hz) lgf value (hex) hgf value (hex) 0 (941, 1336) a3 72 1 (697, 1209) dd 7f 2 (697, 1336) dd 72 3 (697, 1477) dd 67 4 (770, 1209) c8 7f 5 (770, 1336) c8 72 6 (770, 1477) c8 67 7 (852, 1209) b5 7f 8 (852, 1336) b5 72 9 (852, 1477) b5 67 a (697, 1633) dd 5d b (770, 1633) c8 5d c (852, 1633) b5 5d d (941, 1633) a3 5d (941, 1209) a3 7f # (941, 1477) a3 67
1996 dec 18 10 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 6.6 modem frequencies again assuming an oscillator frequency f xtal = 3.58 mhz, the standard modem frequencies can be implemented as in table 8. it is suggested to define the frequency by the hgf register while the lgf register contains 00h, disabling low group frequency generation. table 8 standard modem frequencies and their implementation notes 1. standard is v.21. 2. standard is bell 103. 3. standard is bell 202. 4. standard is v.23. 6.7 musical scale frequencies finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency f xtal = 3.58 mhz (table 9). it is suggested to define the frequency by the hgf register while the lgf contains 00h, disabling low group frequency generation. hgf value (hex) frequency (hz) deviation modem generated (%) (hz) 9d 980 (1) 978.82 - 0.12 - 1.18 82 1180 (1) 1179.03 - 0.08 - 0.97 8f 1070 (2) 1073.33 0.31 3.33 79 1270 (2) 1265.30 - 0.37 - 4.70 80 1200 (3) 1197.17 - 0.24 - 2.83 45 2200 (3) 2192.01 - 0.36 - 7.99 76 1300 (4) 1296.94 - 0.24 - 3.06 48 2100 (4) 2103.14 0.15 3.14 5c 1650 (1) 1655.66 0.34 5.66 52 1850 (1) 1852.77 0.15 2.77 4b 2025 (2) 2021.20 - 0.19 - 3.80 44 2225 (2) 2223.32 - 0.08 - 1.68 table 9 musical scale frequencies and their implementation note 1. standard scale based on a4 @ 440 hz. note hgf value (hex) frequency (hz) standard (1) generated d#5 f8 622.3 622.5 e5 ea 659.3 659.5 f5 dd 698.5 697.9 f#5 d0 740.0 741.1 g5 c5 784.0 782.1 g#5 b9 830.6 832.3 a5 af 880.0 879.3 a#5 a5 923.3 931.9 b5 9c 987.8 985.0 c6 93 1046.5 1044.5 c#6 8a 1108.7 1111.7 d6 82 1174.7 1179.0 d#6 7b 1244.5 1245.1 e6 74 1318.5 1318.9 f6 6d 1396.9 1402.1 f#6 67 1480.0 1482.2 g6 61 1568.0 1572.0 g#6 5c 1661.2 1655.7 a6 56 1760.0 1768.5 a#6 51 1864.7 1875.1 b6 4d 1975.5 1970.0 c7 48 2093.0 2103.3 c#7 44 2217.5 2223.3 d7 40 2349.3 2358.1 d#7 3d 2489.0 2470.4
1996 dec 18 11 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 7 eeprom and timer 2 organization the pca3354c; PCD3354A have 256 bytes of electrically erasable programmable read only memory (eeprom). such non-volatile storage provides data retention without the need for battery backup. in telecom applications, the eeprom is used for storing redial numbers and for short dialling of frequently used numbers. more generally, eeprom may be used for customizing microcontrollers, such as to include a pin code or a country code, to define trimming parameters, to select application features from the range stored in rom. the most significant difference between a ram and an eeprom is that a bit in eeprom, once written to a logic 1, cannot be cleared by a subsequent write operation. successive write accesses actually perform a logical or with the previously stored information. therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. thus, an erase-and-write operation is the eeprom equivalent of a ram write operation. whereas read access times to an eeprom are comparable to ram access times, write and erase accesses are much slower at 5 ms each. to make these operations more efficient, several provisions are available in the pca3354c; PCD3354A. first, the eeprom array is structured into 64 four-byte pages (see fig.4) permitting access to 4 bytes in parallel (write page, erase/write page and erase page). it is also possible to erase and write individual bytes. finally, the eeprom address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. to simplify the erase and write timing, the derivative 8-bit down-counter (timer 2) with reload register is provided. in addition to eeprom timing, timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths.
1996 dec 18 12 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A fig.4 block diagram of the eeprom and timer 2. handbook, full pagewidth mgb783 2 timer 2 reload register eeprom control register eeprom test register eeprom address register 2 : 4 decoder 8 8 timer 2 register (t2) internal bus f0 eeprom latch 0 f1 eeprom latch 1 f2 eeprom latch 2 f3 eeprom latch 3 6 : 64 decoder 256-byte eeprom array (64 4-byte pages) 8 8 8 8 8 8 8 6 t2f set on underflow f xtal 1 480
1996 dec 18 13 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 7.1 eeprom registers 7.1.1 eeprom c ontrol r egister (epcr) the behaviour of the eeprom and timer 2 section is defined by the eeprom control register. see tables 10, 11 and 12. table 10 eeprom control register (address 04h, access type r/w) table 11 description of the epcr bits table 12 mode selection; x = dont care 76543210 stt2 et2i t2f ewp mc3 mc2 mc1 0 bit symbol description 7 stt2 start t2. if stt2 = 0, then timer 2 is stopped; t2 value held. if stt2 = 1, then t2 decrements from reload value. 6 et2i enable t2 interrupt. if et2i = 0, then t2f event cannot request interrupt. if et2i = 1, then t2f event can request interrupt. 5 t2f timer 2 ?ag. set when t2 under?ows (or by program); reset by program. 4 ewp erase or write in progress (ewp). set by program (ewp starts eeprom erase and/or write and timer 2). reset at the end of eeprom erase and/or write. 3 mc3 mode control 3 to 1. these three bits in conjunction with bit ewp select the mode as shown in table 12 . 2 mc2 1 mc1 0 - this bit is set to a logic 0. ewp mc3 mc2 mc1 description 0 0 0 0 read byte 0 0 1 0 increment mode 1 0 1 x write page 1 1 0 0 erase/write page 1 1 1 1 erase page x 0 0 1 not allowed x101 x110
1996 dec 18 14 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 7.1.2 eeprom address register (addr) the eeprom address register determines the eeprom location to which an eeprom access is directed. as a whole, addr auto-increments after read and write cycles to eeprom, but remains fixed after erase cycles. this behaviour generates the correct addr contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. overflow of the 8-bit counter wraps around to zero. table 13 eeprom address register (address 01h, access type r/w) table 14 description of addr bits 7.1.3 eeprom d ata r egister (datr) table 15 eeprom data register (address 03h; access type r/w) table 16 description of datr bits 7.1.4 eeprom test register (tst) the eeprom test register is used for testing purposes during device manufacture. it must not be accessed by the device user. 76543210 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 bit symbol description 7 - this bit is set to a logic 0. 6 to 2 ad6 to ad2 ad2 to ad6 select one of 32 pages. 1 to 0 ad1 to ad0 ad1 and ad0 are irrelevant during erase and write cycles. for read accesses, ad0 and ad1 indicate the byte location within an eeprom page. during page setup, finally, ad0 and ad1 select eeprom latch 0 to 3 whereas ad2 to ad6 are irrelevant. if increment mode (table 12) is active during page setup, the subcounter consisting of ad0 and ad1 increments after every write to an eeprom latch, thus enhancing access to sequential eeprom latches. incrementing stops when eeprom latch 3 is reached, i.e. when ad0 and ad1 are both a logic 1. 76543210 d7 d6 d5 d4 d3 d2 d1 d0 bit symbol description 7 to 0 d7 to d0 the eeprom data register (datr) is only a conceptual entity. a read operation from datr, reads out the eeprom byte addressed by addr. on the other hand, a write operation to datr, loads data into the eeprom latch (see fig.4) defined by bits ad0 and ad1 of addr.
1996 dec 18 15 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 7.2 eeprom latches the four eeprom latches (eeprom latch 0 to 3; fig.4) cannot be read by user software. due to their construction, the latches can only be preset, but not cleared. successive write operations through datr to the eeprom latches actually perform a logical or with the previously stored data in eeprom. the eeprom latches are reset at the conclusion of any eeprom cycle. 7.3 eeprom ?ags the four eeprom flags (f0 to f3; fig.4) cannot be directly accessed by user software. an eeprom flag is set as a side-effect when the corresponding eeprom latch is written through datr. the eeprom flags are reset at the conclusion of any eeprom cycle. 7.4 eeprom macros the instruction sequence used in an eeprom access should be treated as an indivisible entity. erroneous programs result if addr, datr, relr or epcr are inadvertently changed during an eeprom cycle or its setup. special care should be taken if the program may asynchronously divert due to an interrupt. a new access to the eeprom may only be initiated when no write, erase or erase/write cycles are in progress. this can be verified by reading bit ewp (register epcr). for write, erase and erase/write cycles, it is assumed that the timer 2 reload register (relr) has been loaded with the appropriate value for a 5 ms delay, which depends on f xtal (see table 23). the end of a write, erase or erase/write cycle will be signalled by a cleared ewp and by a timer 2 interrupt provided that et2i = 1 and that the derivative interrupt is enabled. 7.5 eeprom access one read, one write, one erase/write and one erase access are defined by bits ewp and mc1 to mc3 in the epcr register; see table 10. read byte retrieves the eeprom byte addressed by addr when datr is read. read cycles are instantaneous. write and erase cycles take 5 ms, however. erase/write is a combination of an erase and a subsequent write cycle, consequently taking 10 ms. as their names imply, write page, erase page and erase/write page are applied to a whole eeprom page. therefore, bits ad0 and ad1 of register addr (see table 13), defining the byte location within an eeprom page, are irrelevant during write and erase cycles. however, write and erase cycles need not affect all bytes of the page. the eeprom flags f0 to f3 (see fig.4) determine which bytes within the eeprom page are affected by the erase and/or write cycles. a byte whose corresponding eeprom flag is zero remains unchanged. with erase page, a byte is erased if its corresponding eeprom flag is set. with write page, data in eeprom latches 0 to 3 (fig.4) are ored to the individual page bytes if and only if the corresponding eeprom flags are set. in an erase/write cycle, f0 to f3 select which page bytes are erased and ored with the corresponding eeprom latches. oring, in this event, means that the eeprom latches are copied to the selected page bytes. the described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. this advantage necessitates a preparation step, called page setup , before the actual erase and/or write cycle can be executed. page setup controls eeprom latches and eeprom flags. this will be described in the sections 7.5.1 to 7.5.5. 7.5.1 p age setup page setup is a preparation step required before write page, erase page and erase/write page cycles. as previously described, these page operations include single-byte write, erase and erase/write as a special event. eeprom flags f0 to f3 determine which page bytes will be affected by the mentioned page operations. eeprom latch 0 to 3 must be preset through datr to specify the write cycle data to eeprom and to set the eeprom flags as a side-effect. obviously, the actual preset value of the eeprom latches is irrelevant for erase page. preset of one, two, three or all four eeprom latches and the corresponding eeprom flags can be performed by repeatedly defining addr and writing to datr (see table 17). if more than one eeprom latch must be preset, the subcounter consisting of ad0 and ad1 can be induced to auto-increment after every write to datr, thus stepping through all eeprom latches. for this purpose, increment mode (table 12) must be selected. auto-incrementing stops at eeprom latch 3. it is not mandatory to start at eeprom latch 0 as in shown in table 18. note that ad2 to ad6 are irrelevant during page setup. they will usually specify the intended eeprom page, anticipating the subsequent page cycle.
1996 dec 18 16 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A from now on, it will be assumed that ad2 to ad6 will contain the intended eeprom page address after page setup. table 17 page setup; preset table 18 page setup; auto-incrementing 7.5.2 r ead byte since addr auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. table 19 read byte 7.5.3 w rite page the write cycle performs a logical or between the data in the eeprom latches and that in the addressed eeprom page. to actually copy the data from the eeprom instruction result mov a, #addr address of eeprom latch mov addr, a send address to addr mov a, #data load write, erase/write or erase data mov datr, a send data to addressed eeprom latch instruction result mov a, #mc2 increment mode control word mov epcr, a select increment mode mov a, #baddr eeprom latch 0 address (ad0 = ad1 = 0) mov addr, a send eeprom latch 0 address to addr mov a, r0 load 1 st byte from register 0 mov datr, a send 1 st byte to eeprom latch 0 mov a, r1 load 2 nd byte from register 1 mov datr, a send 2 nd byte to eeprom latch 1 mov a, r2 load 3 rd byte from register 2 mov datr, a send 3 rd byte to eeprom latch 2 mov a, r3 load 4 th byte from register 3 mov datr, a send 4 th byte to eeprom latch 3 instruction result mov a, #rdaddr load read address mov addr, a send address to addr mov a, datr read eeprom data latches, the corresponding bytes in the page should previously have been erased. the eeprom latches are preset as described in section 7.5.1. the actual transfer to the eeprom is then performed as shown in table 20. the last instruction also starts timer 2. the data in the eeprom latches are ored with that in the corresponding page bytes within 5 ms. a single-byte write is simply a special case of write page. addr auto-increments after the write cycle. if ad0 and ad1 addressed eeprom latch 3 prior to the write cycle, addr will point to the next eeprom page (by bits ad2 to ad6) and to eeprom latch 0 (by bits ad0 and ad1). this allows efficient coding of multi-page write operations. table 20 write page 7.5.4 e rase / write page the eeprom latches are preset as described in section 7.5.1. the page byte corresponding to the asserted flags (among f0 to f3) are erased and re-written with the contents of the respective eeprom latches. the last instruction also starts timer 2. erasure takes 5 ms upon which timer register t2 reloads for another 5 ms cycle for writing. the top cycles together take 10 ms. a single-byte erase/write is simply a special event of erase/write page. addr auto-increments after the write cycle. if ad0 and ad1 addressed eeprom latch 3 prior to the write cycle, addr will point to the next eeprom page (by ad2 to ad6) and to eeprom latch 0 (by ad0 and ad1). this allows efficient coding of multi-page erase/write operations. table 21 erase/write page instruction result mov a, #ewp + mc2 write page control word mov epcr, a start write page cycle instruction result mov a, #ewp + mc3 erase/write page control word mov epcr, a start erase/write page cycle
1996 dec 18 17 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 7.5.5 e rase page the eeprom flags are set as described in section 7.5.1. the corresponding page bytes are erased. the last instruction also starts timer 2. erasure takes 5 ms. a single-byte erase is simply a special case of erase page. note that addr does not auto-increment after an erase cycle. table 22 erase page 7.6 timer 2 timer 2 is a 8-bit down-counter decremented at a rate of 1 480 f xtal . it may be used either for eeprom timing or as a general purpose timer. conflicts between the two applications should be carefully avoided. 7.6.1 t imer 2 for eeprom timing when used for eeprom timing, timer 2 serves to generate the 5 ms intervals needed for erasing or writing the eeprom. at the decrement rate of 1 480 f xtal , the reload value for a 5 ms interval is a function of f xtal . table 23 summarizes the required reload values for a number of oscillator frequencies. timer 2 is started by setting bit ewp in the epcr. the timer register t2 is loaded with the reload value from relr. t2 decrements to zero. for an erase/write cycle, underflow of t2 indicates the end of the erase operation. therefore, timer register t2 is reloaded from relr for another 5 ms interval during which the flagged eeprom latches are copied to the corresponding bytes in the page addressed by addr. instruction result mov a, #ewp + mc3 + mc2 + mc1 erase page control word mov epcr, a start erase page cycle the second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding eeprom cycle. timer 2 is stopped, t2f is set whereas ewp and mc1 to mc3 are cleared. table 23 reload values as a function of f xtal note 1. the reload value is (5 10 - 3 1 480 f xtal ) - 1; f xtal in mhz. 7.6.2 t imer 2 as a general purpose timer when used for purposes other than eeprom timing, timer 2 is started by setting stt2. the timer 2 register t2 (see table 25) is loaded with the reload value from relr. t2 decrements to zero. on underflow, t2 is reloaded from relr, t2f is set and t2 continues to decrement. timer 2 can be stopped at any time by clearing stt2. the value of t2 is then held and can be read out. after setting stt2 again, timer 2 decrements from the reload value. alternatively, it is possible to read t2 on the fly i.e. while timer 2 is operating. f xtal (mhz) reload value (1) (hex) 10a 214 3.58 25 63e 10.74 6f 16 a6
1996 dec 18 18 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 8 derivative interrupts one derivative interrupt event is defined. it is controlled by bits t2f and et2i in the epcr (see tables 10 and 11). the derivative interrupt event occurs when t2f is set. this request is honoured under the following circumstances: no interrupt routine proceeds no external interrupt request is pending the derivative interrupt is enabled et2i is set. the derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing t2f. if the derivative interrupt is not used, t2f may directly be tested by the program. obviously, t2f can also be asserted under program control, e.g. to generate a software interrupt. 9 timing although the pca3354c; PCD3354A operate over a clock frequency range from 1 mhz to 16 mhz, f xtal = 3.58 mhz or 10.74 mhz will usually be chosen to take full advantage of the frequency generator section. 10 reset in addition to the conditions given in the pcd33xxa family data sheet, all derivative registers are cleared in the reset state. 11 idle mode in idle mode, the frequency generator, the eeprom and the timer 2 sections remain operative. therefore, the idle instruction may be executed while an erase and/or write access to eeprom is in progress. 12 stop mode since the oscillator is switched off, the frequency generator, the eeprom and the timer 2 sections receive no clock. it is suggested to clear both the hgf and the lgf registers before entering stop mode. this will cut off the biasing of the internal amplifiers, considerably reducing current requirements. the stop mode must not be entered while an erase and/or write access to eeprom is in progress. the stop instruction may only be executed when ewp in epcr is zero. the timer 2 section is frozen during stop mode. after exit from stop mode by a high level on ce/ t0, timer 2 proceeds from the held state.
1996 dec 18 19 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 13 summary of i/o ports and mask options all standard quasi-bidirectional i/o ports are available; see pcd33xxa family data sheet. port 0: 8 parallel port lines p0.0 to p0.7 port 1: 8 parallel port lines p1.0 to p1.7 port 2: 4 parallel port lines p2.0 to p2.3. in addition to the standard ports, 2 derivative i/o ports are available: derivative port 0: 8 parallel port lines dp0.0 to dp0.7 (register dp0l) derivative port 1: 8 parallel port lines dp1.0 to dp1.7 (register dp1l). the port options and the other rom mask options are listed in table 24. see table 25 for the addresses of dp0l and dp1l. table 24 rom mask options notes 1. if standard (option 1) or push-pull (option 3) output is chosen, the p1.7/mdy output becomes a push-pull output. if open-drain (option 2) is chosen the p1.7/mdy output becomes an open-drain output. 2. if standard (option 1) or push-pull (option 3) output is chosen, the dp1.7/dco output becomes a push-pull output. if open-drain (option 2) is chosen the dp1.7/dco output becomes an open-drain output. function implemented in rom option program/data any mix of instructions and data up to rom size of 8 kbytes. port output p0.0 to p0.7 standard open-drain push-pull p1.0 to p1.6 standard open-drain push-pull p1.7/mdy; note 1 standard open-drain push-pull p2.0 to p2.3 standard open-drain push-pull dp0.0 to dp0.7 standard open-drain push-pull dp1.0 to dp1.6 standard open-drain push-pull dp1.7/dco; note 2 standard open-drain push-pull port state after reset p0.0 to p0.7 set reset - p1.0 to p1.6 set reset - p1.7/mdy set reset - p2.0 to p2.3 set reset - dp0.0 to dp0.7 set reset - dp1.0 to dp1.6 set reset - dp1.7/dco set reset - oscillator transconductance low (g ml ) medium (g mm ) high (g mh ) power-on-reset power-on-reset voltage level: v por 1.2 to 3.6 v in increments of 100 mv; off
1996 dec 18 20 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 14 summary of derivative registers table 25 register map addr. (hex) register 7 6 5 4 3 2 1 0 r/w 00 not used 01 eeprom address register (addr) 0 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w 02 not used 03 eeprom data register (datr) d7 d6 d5 d4 d3 d2 d1 d0 r/w 04 eeprom control register (epcr) stt2 et21 tf2 ewp mc3 mc2 mc1 0 r/w 05 timer 2 reload register (relr) r7 r6 r5 r4 r3 r2 r1 r0 r/w 06 timer 2 register (t2) t2.7 t2.6 t2.5 t2.4 t2.3 t2.2 t2.1 t2.0 r 07 test register (tst) only for test purposes; not to be accessed by the device user 08 to 10 not used 11 high group frequency register (hgf) h7 h6 h5 h4 h3 h2 h1 h0 w 12 low group frequency register (lgf) l7 l6 l5 l4 l3 l2 l1 l0 w 13 clock and melody control register (mdycon) 0 0 0 0 0 dco div3 emo r/w 14 to 2f not used 30 derivative port 0 lines (dp0l) d0.7 d0.6 d0.5 d0.4 d0.3 d0.2 d0.1 d0.0 r 31 derivative port 1 lines (dp1l) d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 d1.1 d1.0 r 32 derivative port 0 ?ip-?op (dp0ff) f0.7 f0.6 f0.5 f0.4 f0.3 f0.2 f0.1 f0.0 r/w 33 derivative port 1 ?ip-?op (dp1ff) f1.7 f1.6 f1.5 f1.4 f1.3 f1.2 f1.1 f1.0 r/w 34 to ff not used
1996 dec 18 21 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 15 limiting values in accordance with the absolute maximum rating system (iec 134). 16 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, it is good practice to take normal precautions appropriate to handling mos devices (see data handbook ic14, section: handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.8 +7.0 v v i all input voltages - 0.5 v dd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma p tot total power dissipation - 125 mw p o power dissipation per output - 30 mw i ss ground supply current - 50 +50 ma t stg storage temperature - 65 +150 c t j operating junction temperature - 90 c
1996 dec 18 22 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 17 dc characteristics v dd = 1.8 to 6 v; v ss =0v; t amb =0to+50 c (pca3354c) or - 25 to +70 c (PCD3354A); all voltages with respect to v ss ; f xtal = 3.58 mhz (g ml ); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage see fig.5 operating note 1 1.8 - 6v ram data retention in stop mode 1.0 - 6v i dd operating supply current see figs 6 and 7; note 2 v dd = 3 v; value hgf or lgf 1 0 - 0.8 1.6 ma v dd = 3 v; value hgf = lgf = 0 - 0.35 0.7 ma v dd =5v; f xtal = 10.74 mhz (g mm ); value hgf or lgf 1 0; div3 = 1 - 2.7 6.2 ma v dd =5v; f xtal = 10.74 mhz (g mm ); value hgf = lgf = 0 - 1.7 4.2 ma v dd =5v; f xtal = 16 mhz (g mh ); value hgf = lgf = 0 - 3.5 - ma i dd(idle) supply current (idle mode) see figs 8 and 9; note 2 v dd = 3 v; value hgf or lgf 1 0 - 0.7 1.4 ma v dd = 3 v; value hgf = lgf =0 - 0.25 0.5 ma v dd =5v; f xtal = 10.74 mhz (g mm ); value hgf or lgf 1 0; div3 = 1 - 2.3 5.5 ma v dd =5v; f xtal = 10.74 mhz (g mm ); value hgf = lgf = 0 - 1.3 3.5 ma v dd =5v; f xtal = 16 mhz (g mh ); value hgf = lgf = 0 - 2.4 - ma i dd(stp) supply current (stop mode) see fig.10; notes 2 and 3 v dd = 1.8 v; t amb =25 c - 1.0 5.5 m a v dd = 1.8 v; t amb = - 25 to +70 c -- 10 m a inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v ss v i v dd - 1 - +1 m a port outputs i ol low level output sink current v dd = 3 v; v o = 0.4 v; see fig.11 0.7 3.5 - ma i oh high level pull-up output source current v dd =3v; v o = 2.7 v; see fig.12 - 10 - 30 -m a v dd =3v; v o = 0 v; see fig.12 -- 140 - 300 m a i oh1 high level push-pull output source current v dd = 3 v; v o = 2.6 v; see fig.13 - 0.7 - 3.5 - ma
1996 dec 18 23 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A notes to the dc characteristics 1. tone output; eeprom erase and write require v dd 3 2.5 v: a) tone output requires f xtal < 4 mhz in case div3 = 0. b) tone output requires f xtal < 12 mhz in case div3 = 1. 2. v il =v ss ; v ih =v dd ; open-drain outputs connected to v ss ; all other outputs open: a) maximum values: external clock at xtal1 and xtal2 open-circuit. b) typical values: t amb =25 c; crystal connected between xtal1 and xtal2. 3. v il =v ss ; v ih =v dd ; reset, t1 and ce/ t0 at v ss ; crystal connected between xtal1 and xtal2; open-drain outputs connected to v ss ; all other outputs open. 4. values are specified for dtmf frequencies only (cept). 5. related to the low group frequency (lgf) component (cept). 6. after final testing the value of each eeprom bit is typically logic 1. 7. verified on sampling basis. 8. v por is an option chosen by the user. depending on its value, it may restrict the supply voltage range. 9. each device is tested on the condition: v dd(min) PCD3354A - 0.5 0 +0.5 v v por power-on-reset level note 9; for pca3354c 1.7 2.0 2.3 v oscillator (see fig.16) g ml low transconductance v dd = 5 v 0.2 0.4 1.0 ms g mm medium transconductance v dd = 5 v 0.9 1.6 3.2 ms g mh high transconductance v dd = 5 v 3 4.5 9.0 ms r f feedback resistor 0.3 1.0 3.0 m w symbol parameter conditions min. typ. max. unit f d f
1996 dec 18 24 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A fig.5 maximum clock frequency (f xtal ) as a function of supply voltage (v dd ). handbook, halfpage mla493 v dd (v) 13 5 7 f xtal (mhz) 12 9 6 3 0 15 18 guaranteed operating range fig.6 typical operating supply current (i dd ) as a function of supply voltage (v dd ). measured with crystal between xtal1 and xtal2. handbook, halfpage 1 6 4 2 0 35 v dd (v) 7 mgb813 i dd (ma) 16 mhz hgf = lgf = 0 g mh ?5 o c to 70 o c 10.7 mhz hgf = lgf = 0 g mm 3.58 mhz hgf lgf g ml 3.58 mhz hgf = lgf = 0 g ml 10.7 mhz hgf lgf = 0 g mm fig.7 typical operating supply current (i dd ) as a function of clock frequency (f xtal ). measured with function generator on xtal1. handbook, halfpage 6 0 2 2 4 1 mgb828 10 10 i dd (ma) f xtal (mhz) 3 v 5 v fig.8 typical supply current in idle mode (i dd(idle) ) as a function of supply voltage (v dd ). measured with crystal between xtal1 and xtal2. handbook, halfpage 1 6 4 2 0 35 v dd (v) 7 mgb814 i dd(idle) (ma) 16 mhz hgf = lgf = 0 g mh ?5 o c to 70 o c 10.7 mhz hgf = lgf = 0 g mm 3.58 mhz hgf lgf g ml 3.58 mhz hgf = lgf = 0 g ml 10.7 mhz hgf lgf = 0 g mm
1996 dec 18 25 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A fig.9 typical supply current in idle mode (i dd(idle) ) as a function of clock frequency (f xtal ). measured with function generator on xtal1. handbook, halfpage 6 0 2 2 4 1 mgb830 10 10 i dd(idle) (ma) f xtal (mhz) 3 v 5 v fig.10 typical supply current in stop mode (i dd(stp) ) as a function of supply voltage (v dd ). handbook, halfpage 1 6 4 3 1 5 2 0 35 v dd (v) 7 mgb826 i dd(stp) ( m a) fig.11 typical low level output sink current (i ol ) as a function of supply voltage (v dd ). v o = 0.4 v. handbook, halfpage 1 12 8 4 0 35 v dd (v) 7 mgb831 i ol (ma) fig.12 typical high level pull-up output source current (i oh ) as a function of supply voltage (v dd ). handbook, halfpage 1 - 300 - 200 - 100 0 3 i oh ( m a) 5 v dd (v) 7 mgb832 v o = 0 v v o = 0.9v dd
1996 dec 18 26 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A fig.13 typical high level push-pull output source current (i oh1 ) as a function of supply voltage (v dd ). v o =v dd - 0.4 v. handbook, halfpage 1 - 12 - 8 - 4 0 35 v dd (v) 7 mgb833 i oh1 (ma) fig.14 tone output test circuit. handbook, halfpage mgb835 10 k w tone 50 pf 1 m f device type number (1) v dd v ss (1) device type number: pca3354c or PCD3354A. fig.15 typical power-on-reset level (v por ) as function of ambient temperature (t amb ). handbook, halfpage - 25 6 4 2 0 25 75 70 t amb ( c) 125 mgd495 v dd (v) v por = 1.3 v v por = 2.0 v fig.16 typical transconductance (g m ) as a function of supply voltage (v dd ). handbook, halfpage 135 v dd (v) 7 10 1 mgb818 1 10 g ml g mm g mh g m (ms)
1996 dec 18 27 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 18 ac characteristics v dd = 1.8 to 6 v; v ss =0v; t amb =0to+50 c (pca3354c) or - 25 to +70 c (PCD3354A); all voltages with respect to v ss ; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit t r rise time all outputs v dd = 5 v; t amb =25 c; c l =50pf - 30 - ns t f fall time all outputs - 30 - ns f xtal clock frequency see fig.5 1 - 16 mhz
1996 dec 18 28 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 19 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 19.2 18.2 1.2 0.9 2.4 1.8 7 0 o o 0.15 2.35 0.1 0.3 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2.0 1.2 sot205-1 92-11-17 95-02-04 d (1) (1) (1) 14.1 13.9 h d 19.2 18.2 e z 2.4 1.8 d b p e q e a 1 a l p q detail x l (a ) 3 b 11 y c d h b p e h a 2 v m b d z d a z e e v m a x 1 44 34 33 23 22 12 133e01a pin 1 index w m w m 0 5 10 mm scale qfp44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm sot205-1 a max. 2.60
1996 dec 18 29 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 20 soldering 20.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 20.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 20.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 dec 18 30 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A 21 definitions 22 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 dec 18 31 philips semiconductors product speci?cation 8-bit microcontrollers with dtmf generator and 256 bytes eeprom pca3354c; PCD3354A notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417021/1200/04/pp32 date of release: 1996 dec 18 document order number: 9397 750 01082

▲Up To Search▲

Price & Availability of PCD3354A

	To Download PCD3354A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .